Programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs), are user-programmable integrated circuits that can be programmed to implement user-defined logic circuits. In a typical architecture, an FPGA includes an array of configurable logic blocks (CLBs) surrounded by programmable input/output blocks (IOBs). A hierarchy of programmable routing resources interconnects the CLBs and IOBs. Loading a configuration bitstream into configuration memory cells of the FPGA customizes these CLBs, IOBs, and programmable routing resources. Additional resources, such as multipliers, memory, and application-specific circuits may also be included.
PLDs are growing ever larger as vendors attempt to satisfy customer demand for PLDs capable of performing ever more complex tasks. Unfortunately, as chip size increases, so too does the probability of finding a defect on a given chip. The process yield therefore decreases with PLD complexity, making already expensive PLDs still more expensive.
PLDS are not design specific, but instead afford users (e.g., circuit designers) the ability to instantiate an almost unlimited number of circuit variations. Not knowing in advance the purpose to which a given PLD will be dedicated places a heavy burden on the quality and reliability of the PLD because PLD vendors must verify the functionality of any feature that might be used. To avoid disappointing customers, PLD manufacturers discard PLDS that include even relatively minor defects.
PLD defects can be categorized in two general areas: gross defects that render the entire PLD useless or unreliable, and localized defects that damage a relatively small percentage of the PLD. It has been found that, for some large chips, close to two thirds of the chips on a given wafer may be discarded because of localized defects. Considering the costs associated with manufacturing large integrated circuits, discarding a large percentage of PLD chips has very significant adverse economic impact on PLD manufacturers.